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FUJITSU SEMICONDUCTOR DATA SHEET
DS06-20110-5E
Semicustom
CMOS
Embedded array
CE81 Series
DESCRIPTION
The CE81 series 0.18 m CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed and low power consumption. This series incorporates up to 34 million gates which have a gate delay time of 12 ps, resulting in both integration and speed about three times higher than conventional products. In addition, CE81 series can operate at a power-supply voltage of down to 1.1 V, substantially reducing power consumption.
FEATURES
* * * * * * * * * * * * * * * * Technology : 0.18 m silicon-gate CMOS, 3- to 5-layer wiring Supply voltage : + 1.8 V 0.15 V (normal) to + 1.1 V 0.1 V Junction temperature range : -40 to +125 C Gate delay time : tpd = 12 ps (1.8 V, inverter, F/O = 1) Gate power consumption : Pd = 8 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1) High-load driving capability : IOL = 2/4/8/12 mA mixable Output buffer cells with noise reduction circuits Inputs with on-chip input pull-up/pull-down resistors (33 k typical) and bidirectional buffer cells Buffer cells dedicated to crystal oscillator Special interface : P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, and others (including those under development) IP macros : CPU, DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others (including those under development) Capable of incorporating compiled cells (RAM/ROM/multiplier, and others) Configurable internal bus circuits Advanced hardware/software co-design environment Short-term development using a timing driven layout tool Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time (Continued)
Copyright(c)1999-2006 FUJITSU LIMITED All rights reserved
CE81 Series
(Continued) * Hierarchical design environment for supporting large-scale circuits * Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture * Support for memory (RAM/ROM) SCAN * Support for memory (RAM) BIST * Support for boundary SCAN * Support for path delay test * A variety of package options (TQFP, HQFP, EBGA, FBGA, TAB-BGA, LQFP)
MACRO LIBRARY (Including macros being prepared)
1.
* * * * * * * * * *
Logic cells (about 800 types)
Adder AND-OR Inverter Clock Buffer Latch NAND AND NOR SCAN Flip Flop ENOR AND-OR * * * * * * * * * * Decoder Non-SCAN Flip Flop Inverter Buffer OR-AND Inverter OR Selector BUS Driver EOR Others
2. IP macros
CPU/DSP Interface macro Multimedia processing macros Mixed signal macros Compiled macros PLL FR, SPARClite, standard CPU (under preparation) Communications DSP, DSP for AV PCI, IEEE1394, USB, IrDA, etc. JPEG, MPEG, etc. ADC, DAC, OPAMP, etc. RAM, ROM, multiplier, adder, multiplier-accumulator, etc. Analog PLL, digital PLL
3. Special I/O interface macros
* T-LVTTL * LVDS * IEEE1394 * SSTL * PCI * HSTL * AGP * P-CML * USB
2
CE81 Series
CHIP STRUCTURE
The chip layout of the CE81 series consists of two major areas : chip peripheral area and basic cell area. The chip peripheral area contains the input/output buffer cells for interfacing with external devices and the associated bonding pads. The basic cell area contains some of input/output buffer cells, the unit cells and the compiled cells. * Chip configuration
Bonding pad
I/O buffer cell
Basic cell area
3
CE81 Series
COMPILED CELLS
Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CE81 series has the following types of compiled cells (Note that each macro is different in word/bit range depending on the column type) .
1. Clock synchronous single-port RAM (1 address : 1 RW)
* High density/Partial write type Column type Memory capacity 4 16 * High speed type Column type 8 16 to 72 K 64 to 72 K Word range 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit Bit Bit
Memory capacity 256 to 144 K
Word range 64 to 2 K
Bit range 4 to 72
Unit Bit
* Large scale partial write type Column type Memory capacity 16 24.5 K to 1179 K
Word range 4 to 16 K
Bit range 6 to 72
Unit Bit
2. Clock synchronous dual-port RAM (2 addresses : 1 RW, 1 R)
* High density/Partial write type Column type Memory capacity 4 16 16 to 72 K 64 to 72 K Word range 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit Bit Bit
3. Clock synchronous register file (3 addresses : 1 W, 2 R)
Column type 1 Memory capacity 4608 Word range 4 to 64 Bit range 1 to 72 Unit Bit
4. Clock synchronous register file (4 addresses : 2 W, 2 R)
Column type 1 Memory capacity 4608 Word range 4 to 64 K Bit range 1 to 72 Unit Bit
5. Clock synchronous ROM (1 addresses : 1 R)
Column type 16 Memory capacity 256 to 512 K Word range 128 to 4 K Bit range 2 to 128 Unit Bit
6. Clock synchronous delay line memory (2 addresses : 1 W, 1 R)
Column type 8 16 32 4 Memory capacity 256 to 32 K 384 to 32 K 512 to 32 K Word range 32 to 1 K 64 to 2 K 128 to 4 K Bit range 8 to 32 6 to 16 4 to 8 Unit Bit Bit Bit
CE81 Series
ABSOLUTE MAXIMUM RATINGS
Rating Min -0.5 -0.5 -0.5 -55 -40 Max +2.5 *2 +4.0 *3 VDD+0.5 ( 2.5 V) *2 VDD+0.5 ( 4.0 V) *3 VDD+0.5 ( 2.5 V) *2 VDD+0.5 ( 4.0 V) *3 +125 +125 4 Clock Input * : 200 Normal Input : 100 100 3000/RO 10 *7
5
Parameter Supply voltage*1 Input voltage*1 Output voltage*1 Storage temperature Junction temperature Output current *4 Input signal transmitting rate Output signal transmitting rate Output load capacitance Continuous time of indefinite input signal Supply pin current
Symbol VDD VI VO Tst Tj IO RI RO CO tZ ID
Unit V V V C C mA Mbps *6 Mbps *6 pF ms mA
*1 : The parameter is based on VSS = 0 V. *2 : Internal gate part in case of signal power supply or dual power supply *3 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply *4 : DC current which continues more than 10 ms, or average DC current *5 : In case of using I/O cell for clock input *6 : bps = bit per second *7 : Supply pin current for one VDD/GND pin Maximum current [mA] Standard source Additional source
68 39 68 34 43 68 39 68 34 30
Frame
Source type
VDDE, VDDI, VDD, VSS
Number of layer
4, 5 3
YS/S, YI/I
VDDE VDDI, VDD, VSS
A B
VDDE, VDDI, VDD, VSS VDDE, VDDI, VDD, VSS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
5
CE81 Series
RECOMMENDED OPERATING CONDITIONS
* Single power supply (VDD = + 1.8 V 0.15 V) Parameter Supply voltage (1.8 V supply voltage) "H" level input voltage (1.8 V CMOS) "L" level input voltage (1.8 V CMOS) Junction temperature Symbol VDD VIH VIL Tj Value Min 1.65 VDD x 0.65 -0.3 -40 Typ 1.8 Max 1.95 VDD + 0.3 VDD x 0.35 +125 (VSS = 0 V) Unit V V V C
* Dual power supply (VDDE = + 3.3 V 0.3 V, VDDI = + 1.8 V 0.15 V) Parameter Supply voltage "H" level input voltage "L" level input voltage Junction temperature 1.8 V supply voltage 3.3 V supply voltage 1.8 V CMOS 3.3 V CMOS 1.8 V CMOS 3.3 V CMOS Symbol VDDI VDDE VIH VIL Tj Value Min 1.65 3.0 VDD x 0.65 2.0 -0.3 -0.3 -40 Typ 1.8 3.3 Max 1.95 3.6 VDDI + 0.3 VDDE + 0.3 VDD x 0.35 +0.8 +125
(VSS = 0 V) Unit V V V C
* Dual power supply (VDDE = + 3.3 V 0.3 V, VDDI = + 1.5 V 0.1 V / + 1.1 V 0.1 V) Parameter Symbol VDDE Supply voltage "H" level input voltage 3.3 V CMOS "L" level input voltage Junction temperature 3.3 V CMOS VDDI VIH VIL Tj Value Min 3.0 1.0 1.4 2.0 -0.3 -40 Typ 3.3 1.1 1.5 Max 3.6 1.2 1.6 VDDE + 0.3 +0.8 +125
(VSS = 0 V) Unit V V V V V C
6
CE81 Series
* Dual power supply (VDDE = + 2.5 V 0.2 V, VDDI = + 1.8 V 0.15 V) Parameter Supply voltage "H" level input voltage "L" level input voltage Junction temperature 1.8 V CMOS 2.5 V CMOS 1.8 V CMOS 2.5 V CMOS Symbol VDDE VDDI VIH VIL Tj Value Min 2.3 1.65 VDDI x 0.65 1.7 -0.3 -0.3 -40 Typ 2.5 1.8 Max 2.7 1.95 VDDI + 0.3 VDDE + 0.3 VDDI x 0.35 +0.7 +125 (VSS = 0 V) Unit V V V V V V C
* Dual power supply (VDDE = + 2.5 V 0.2 V, VDDI = + 1.5 V 0.1 V / + 1.1 V 0.1 V) Parameter Symbol VDDE Supply voltage "H" level input voltage 2.5 V CMOS "L" level input voltage 2.5 V CMOS Junction temperature VDDI VIH VIL Tj Value Min 2.3 1.0 1.4 1.7 -0.3 -40 Typ 2.5 1.1 1.5 Max 2.7 1.2 1.6 VDDE + 0.3 +0.7 +125
(VSS = 0 V) Unit V V V V V C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
7
CE81 Series
ELECTRICAL CHARACTERISTICS
1. DC CHARACTERISTICS
* Static supply current (single power supply/Dual power supply) A frame Frame CATLG value [mA] A4 0.5 A5 0.7 A6 1 A7 1.4 A8 2 A9 2.6 AA 3.3 AB 4 AC 4.6 AD 5.3 AE 6.6
S frame Frame CATLG value [mA]
SA 3.7
SB 4.4
SC 5
SD 5.8
SE 7.1
SF 9.2
SG 10.9
I frame Frame CATLG value [mA]
I1 0.3
I2 0.4
I3 0.6
I4 0.7
I5 0.8
I6 1.2
I7 1.5
I8 2
I9 2.8
IA 3.4
Note : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = + 25 C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resister or a crystal oscillator buffer is used. The above values may not be guaranteed when a High-speed cell library is used. * Single power supply : VDD = 1.8 V Parameter Supply current "H" level output voltage "L" level output voltage "H" level output V-I characteristics "L" level output V-I characteristics Input leakage current Pull-up/pull-down resistance Symbol IDDS VOH VOL IL RP
(VDD = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C) Conditions IOH = -100 A IOL = 100 A VDD = 1.8 V0.15 V VDD = 1.8 V0.15 V Pull-up VIL = 0 Pull-down VIH = VDD Value Min VDD - 0.2 0 Typ 18 Max * VDD 0.2 5 Unit mA V V A k
* : Refer to the table on the previous page "Static supply current (single power supply/Dual power supply) ".
8
CE81 Series
* Dual power supply : VDDE = 3.3 V, VDDI = 1.8 V / 1.5 V / 1.1 V (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V / 1.5 V 0.1 V / 1.1 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter Supply current Symbol IDDS VOH4 "H" level output voltage VOH2 VOL4 "L" level output voltage VOL2 Conditions 3.3 V output IOH = -100 A 1.8 V output IOH = -100 A 3.3 V output IOL = 100 A 1.8 V output IOL = 100 A 3.3 V VDDE = 3.3 V0.3 V 1.8 V VDDI = 1.8 V0.15 V 3.3 V VDDE = 3.3 V0.3 V 1.8 V VDDE = 1.8 V0.15 V 1.8 V Pull-up/pull-down resistance RP
Pull up VIL = 0 Pull down VIH = VDDI
Value Min VDDE - 0.2 VDDI - 0.2 0 0 Typ *2 *2
18
Max *1 VDDE VDDI 0.2 0.2
Unit mA V V V V
"H" level output V-I characteristics
"L" level output V-I characteristics
IOL
Input leakage current
IL
5
A
3.3 V
Pull up VIL = 0 Pull down VIH = VDDE 10 33 80
k
*1 : Refer to the table on the previous page "Static supply current (single power supply/Dual power supply) ". *2 : Refer to the "* V-I Characteristics" Fig. 1, Fig. 2.
9
CE81 Series
* Dual power supply : VDDE = 2.5 V, VDDI = 1.8 V / 1.5 V / 1.1 V (VDDE = 2.5 V 0.2 V, VDDI = 1.8 V 0.15 V / 1.5 V 0.1 V / 1.1 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter Supply current Symbol IDDS VOH3 "H" level output voltage VOH2 VOL3 "L" level output voltage VOL2 Conditions 2.5 V output IOH = -100 A 1.8 V output IOH = -100 A 2.5 V output IOL = 100 A 1.8 V output IOL = 100 A 2.5 V VDDE = 2.5 V0.2 V 1.8 V VDDI = 1.8 V0.15 V 2.5 V VDDE = 2.5 V0.2 V 1.8 V VDDI = 1.8 V0.15 V 1.8 V Pull-up/pull-down resistance RP
Pull up VIL = 0 Pull down VIH = VDDI
Value Min VDDE - 0.2 VDDI - 0.2 0 0 Typ
18
Max * VDDE VDDI 0.2 0.2
Unit mA V V V V
"H" level output V-I characteristics
IOH
"L" level output V-I characteristics
IOL
Input leakage current
IL
5
A
2.5 V
Pull up VIL = 0 Pull down VIH = VDDE
k
25
* : Refer to the table on the previous page "Static supply current (single power supply/Dual power supply) ".
10
CE81 Series
* V-I Characteristics Min : Process = Slow, Tj = + 125 C, VDD = 3.6 V Typ : Process = Typical, Tj = + 25 C, VDD = 3.3 V Max : Process = Fast, Tj = -40 C, VDD = 3.0 V
VOH-VDD (V) -4.0 -3.0 -2.0 -1.0 0.0 0 -20 -40 -60 -80 Max -100 -120 IOH (mA) IOL (mA) 120 Max Min 100 80 60 40 Min 20 0 0.0 1.0 2.0 VOL (V) 3.0 4.0
Typ
Typ
Fig.1 V-I characteristics (3.3 V normal I/O L, M type) Min : Process = Slow, Tj = + 125 C, VDD = 3.6 V Typ : Process = Typical, Tj = + 25 C, VDD = 3.3 V Max : Process = Fast, Tj = -40 C, VDD = 3.0 V
VOH-VDD (V) -4.0 -3.0 -2.0 -1.0 0.0 0 -20 Min -40 IOH (mA) IOL (mA) -60 -80 -100 -120 -140 Max -160 160 140 120 100 80 60 Min 40 20 0 0.0 2.0 VOL (V) 3.0 4.0 Typ Max
Typ
1.0
Fig.2 V-I characteristics (3.3 V normal I/O H, V type)
11
CE81 Series
2. AC Characteristics
Parameter Delay time Symbol tpd*1
(VDD = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C) Rating Min typ*2 x tmin*3 Typ typ*2 x ttyp*3 Max typ*2 x tmax*3 Unit ns
*1 : Delay time = propagation delay time, Enable time, Disable time *2 : "typ" is calculated based on the cell specification. *3 : Measurement conditions. Measurement condition VDD = 2.5 V0.2 V, VSS = 0 V, Tj = -40 C to +125 C VDD = 1.8 V0.15 V, VSS = 0 V, Tj = -40 C to +125 C VDD = 1.5 V0.1 V, VSS = 0 V, Tj = -40 C to +125 C tmin 0.60 0.84 1.14 ttyp 1.00 1.57 2.22 tmax 1.64 2.84 4.09
Note : tpd max is calculated according to the maximum junction temperature (Tj) .
INPUT/OUTPUT PIN CAPACITANCE
(f = 1 MHz, VDD = VI = 0 V, Ta = +25 C) Parameter Input pin Output pin I/O pin Symbol CIN COUT CI/O Value Max 16 Max 16 Max 16 Unit pF pF pF
Note : Capacitance varies according to the package and the location of the pin.
DESIGN METHOD
Linking a floor plan tool and a logic synthesis tool enables automatic circuit optimization using floor plan information. In addition, also available are CDDM (Clock Driven Design Method) clock tree synthesis tools using floor plan information. Using floor plan information at a pre-layout stage prevents major problems with setup and hold timings which can occur after layout. Using a hierarchical layout method to support larger-scale circuit design considerably shortens the overall design cycle time.
12
CE81 Series
PACKAGES
The table below lists the package types available and the reference number of gates used. Consult Fujitsu for the combination of each package and the availability. * Number of gates used and package types
Package & Pin Count T A B B G A E B G A H Q F P T Q F P L Q F P F B G A 304 352 480 560 660 720 576 660 672 208 240 256 304 304 100 120 Pin Pitch (mm) 0.80 0.80 1.00 1.00 1.00 1.00 1.27 1.00 1.27 0.50 0.50 0.40 0.50 0.50 0.50 0.40 1098k 2085k 3764k 4712k 15158k 514k 514k 0 2000k 4000k 6000k 8000k 10000k 12000k 14000k 16000k 18000k 20000k
891k 1254k 1905k 2689k 3609k 9129k 5982k 12727k 7952k
144 176 208 112 176 192 240 272 288
0.50 0.50 0.50 0.80 0.80 0.80 0.50 0.80 0.75
722k 963k 1098k 514k 722k 1098k 2697k 1550k 2697k
Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu.
13
CE81 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
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